Design Verification Engineer- PCIe

Description: The Design Verification (DV) engineer at Client’s is involved in the functional verification of PCIe controller and PCIe-phy at block, sub-system and MLSoC level. Will also be involved in PCIe bring-up and debug on emulator. Generate required PCIe controller and phy initialization (register programming code sequence) for PCIe Required Background: BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring-up/debug. Very good current working experience of UVM and System Verilog based verification methodology is a must. Working experience on PCIe protocols Gen4/5. Working experience on PCIe bring-up and debug on Silicon is a plus. Past working experience on UCIe protocols is a plus. Proficiency in C/C++/Python programming is a plus. Good debug and problem solving skill.