RTL Design Engineer | Remote

Work Snapshot Type: Full-time position Location: Remote Commitment: ~40 hours/week What You’ll Be Doing Design and develop digital RTL components for advanced chip design workflows Perform design verification using SystemVerilog and UVM methodologies Build and debug testbenches, simulation environments, and verification infrastructure Analyze and debug RTL issues using simulation logs and waveform tools Work across ASIC design flows including synthesis, timing analysis, CDC, and DFT-aware design Collaborate with cross-functional teams across architecture, verification, and implementation Utilize AI-assisted tools to enhance chip design, verification, and debugging workflows Document design specifications, verification plans, and technical trade-offs clearly What We’re Looking For Strong experience in RTL design or design verification engineering Strong experience in Verilog, SystemVerilog, and UVM methodologies Strong understanding of digital design fundamentals including FSMs, datapaths, pipelines, and bus protocols Strong experience in ASIC design and verification flows including synthesis, timing, CDC, and coverage analysis Familiarity with EDA tools for simulation, debugging, and verification workflows Ability to debug complex RTL and verification issues effectively Strong communication and collaboration skills across engineering teams Experience with AMBA protocols such as AXI, AHB, or APB is a plus Background in domains such as CPU, GPU, ML accelerators, networking, or SoC design is a plus Familiarity with formal verification or coverage-driven verification methodologies is a plus How To Apply Upload resume Interview Submit form